Author :
Coquand, R. ; Monfray, Stephane ; Barraud, S. ; Samson, M.P. ; Arvet, C. ; Pradelles, J. ; Bustos, Javier ; Martin, Larry K. ; Tosti, L. ; Perreau, P. ; Hartmann, J.M. ; Lacord, J. ; Casse, M. ; Clement, L. ; Pofelski, A. ; Lepinay, K. ; Ghibaudo, Gerard
Abstract :
This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal SiO2/Poly-Si:P gate stack and the first electrical results obtained with this technique are presented. The good nMOS performances (ION=1mA/μm at VG=VT+0.7V) with excellent electrostatics (SS down to 62mV/dec and DIBL below 10mV/V at LG=80nm) are paving the way to the ultimate CMOS architecture. To meet all requirements of low-power SoCs, we also demonstrate the feasibility of fabricating such devices with High-K Metal-Gate (HK-MG) stack and their possible co-integration with FDSOI structures.
Keywords :
CMOS integrated circuits; lithography; three-dimensional integrated circuits; FDSOI structures; HSQ resist exposition through; cointegration; electrostatics; gate all around nanowire transistors; high k metal gate stack; innovative through silicon 3D lithography; low power SoC; nMOS performances; planar double gate transistors; self aligned multigate devices; silicon channel; ultimate CMOS architecture; Lithography; Logic gates; Performance evaluation; Silicon; Silicon compounds; Silicon germanium; Very large scale integration;
