DocumentCode
629160
Title
Neural network based on a three-terminal ferroelectric memristor to enable on-chip pattern recognition
Author
Kaneko, Yuya ; Nishitani, Yu. ; Ueda, Makoto ; Tsujimura, Ayumu
Author_Institution
Adv. Technol. Res. Labs., Panasonic Corp., Kyoto, Japan
fYear
2013
fDate
11-13 June 2013
Abstract
We demonstrate on-chip pattern recognition in a neural network circuit using a non-volatile memory for the first time. The synapse chip of the neural network consists of a stack of CMOS circuits and three-terminal ferroelectric memristors (3T-FeMEMs). By using the analog and non-volatile conductance change of the 3T-FeMEM as a synaptic weight, the matrix patterns are learned. Even when an incomplete pattern is input to the neural network circuit, it automatically recognizes the original pattern.
Keywords
memristors; neural nets; pattern recognition; 3T-FeMEM; CMOS circuits; matrix patterns; neural network circuit; nonvolatile conductance change; nonvolatile memory; on chip pattern recognition; synapse chip; synaptic weight; three terminal ferroelectric memristors; Biological neural networks; CMOS integrated circuits; Electric potential; Logic gates; Neurons; Nonvolatile memory; Pattern recognition; ferroelectric; memristor; neural network; non-volatile memory; pattern recognition;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location
Kyoto
ISSN
0743-1562
Print_ISBN
978-1-4673-5226-0
Type
conf
Filename
6576659
Link To Document