Title :
Pipelined R22SDF, R4SDC FFT architecture via folding transformation
Author :
Suruthi, S. ; Arulkumar, M.
Author_Institution :
Dept. of ECE, Srinivasan Eng. Coll., Perambalur, India
Abstract :
A novel method for designing a pipelined parallel architectures for the computation of FFT (Fast Fourier Transform) with the procedure of folding transformation and register minimization techniques is presented. The functionality of designed architecture is verified by simulation in hardware description language VHDL. Further architectures namely R22SDF(Radix22 Single path delay feedback), R4SDC (Radix4 Single path Delay Commutator) through folding technique with reduced hardware complexity is proposed. A comparison is made between the earlier and proposed architecture.
Keywords :
fast Fourier transforms; hardware description languages; parallel architectures; signal processing; R4SDC FFT architecture; Radix22 single path delay feedback; Radix4 single path delay commutator; VHDL; digital signal processing; fast Fourier transform; folding transformation; hardware description language; pipelined R22SDF; pipelined parallel architectures; register minimization techniques; Algorithm design and analysis; Complexity theory; Computer architecture; Delays; Hardware; Minimization; Registers; Fast Fourier Transform; Flow Graph; Folding Transformation; Radix 22; Register Minimization Technique Pipelining;
Conference_Titel :
Communications and Signal Processing (ICCSP), 2013 International Conference on
Conference_Location :
Melmaruvathur
Print_ISBN :
978-1-4673-4865-2
DOI :
10.1109/iccsp.2013.6577002
