Power efficiency of 3D vs 2D ICs

Author

Chrzanowska-Jeske, Malgorzata ; Ahmed, Moataz A.

fYear

2013

fDate

20-21 June 2013

Firstpage

1

Lastpage

4

Abstract

3D integration is considered as one of the most promising solutions to improve energy efficiency of heterogeneous ICs. We use floorplannning tools to evaluate power consumption related to inter-block connections for digital ICs implemented as 2D and 3D systems. We focus on 3D stacking using through-silicon-vias (TSVs). We evaluate contributions of wires, buffers and TSVs based on information available on the floorplannig level that include netlist, and positions of circuit blocks and TSV islands. Our results show that reduction in dynamic power could be achieved.

Keywords

digital integrated circuits; energy conservation; integrated circuit layout; three-dimensional integrated circuits; 2D IC system; 3D IC system; 3D stacking; TSV; buffer; circuit block position; digital IC implementation; energy efficiency; floorplannning tool; heterogeneous IC; interblock connection; power consumption; power efficiency; through-silicon-vias; wire; Capacitance; Power demand; Power dissipation; Stress; Through-silicon vias; Wires; 3D-IC; Through-Silicon-Vias (TSVs); buffers; power efficiency; wirelength;

fLanguage

English

Publisher

ieee

Conference_Titel

Faible Tension Faible Consommation (FTFC), 2013 IEEE

Conference_Location

Paris

Print_ISBN

978-1-4673-6105-7

Type

conf

DOI

10.1109/FTFC.2013.6577778

Filename

6577778