A 9b, 1.12ps resolution 2.5b/stage pipelined time-to-digital converter in 65nm CMOS using time-register

This paper presents a 2.5b/stage pipelined time-to-digital converter (TDC). For pipelined operation, a novel time-register is proposed which is capable of storing and adding time information with a clock signal. Together with a time-amplifier, a 9-bit synchronous pipelined TDC is implemented which consists of three 2.5b stages and a 3b flash TDC. A prototype chip fabricated in 65nm CMOS achieves 1.12ps of time resolution at 250Msps while consuming 15.4mW, which results in the best FoM among the state-of-the-art TDCs.