• DocumentCode
    629980
  • Title

    A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

  • Author

    Nandwana, Romesh Kumar ; Saxena, Shanky ; Elshazly, Amr ; Mayaram, K. ; Hanumolu, Pavan Kumar

  • Author_Institution
    Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
  • fYear
    2013
  • fDate
    12-14 June 2013
  • Abstract
    A scrambling TDC is proposed to mitigate dithering jitter accumulation in clock multipliers with low reference frequencies. Fabricated in a 90nm CMOS process, the prototype operates with a 1.25MHz reference clock and generates 160MHz and 2.56GHz output clocks with a long-term absolute jitter of 2.7psrms and 6.28psrms, respectively.
  • Keywords
    CMOS logic circuits; clocks; jitter; multiplying circuits; CMOS process; digital clock multiplier; frequency 1.25 MHz; frequency 160 MHz; frequency 2.5 GHz; jitter accumulation; power 5.4 mW; scrambling TDC; Bandwidth; Clocks; Educational institutions; Frequency division multiplexing; Jitter; Oscillators; Phase locked loops;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2013 Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4673-5531-5
  • Type

    conf

  • Filename
    6578645
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=629980