High-gain wide-bandwidth capacitor-less low-dropout regulator with zero insertion utilizing frequency response of inner loops

Introducing a new zero insertion technique, a proposed capacitor-less LDO has a wide bandwidth of 3.0MHz at 150mA with bias current of 40μA and the best line and load regulations of 0.0024%/V and 0.0000417%/mA, respectively, compared with previously reported LDOs. This chip has 100mV dropout voltage when using the main PMOS of a 76,800um/0.5um I/O transistor. The measured PSRR was 57.75dB at 10 kHz and 29pF of total capacitance was used with the IC size of 0.28mm².