• DocumentCode
    629992
  • Title

    A 1062Mpixels/s 8192×4320p High Efficiency Video Coding (H.265) encoder chip

  • Author

    Sung-Fang Tsai ; Chung-Te Li ; Hsuan-Hung Chen ; Pei-Kuei Tsung ; Kuan-Yu Chen ; Liang-Gee Chen

  • Author_Institution
    Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2013
  • fDate
    12-14 June 2013
  • Abstract
    A single-chip HEVC (H.265) 8192×4320p encoder is implemented on a 25mm2 die with 28nm process. It dissipates 708mW at 312MHz for 8192×4320p encoding. Frame-level pipelining reduces 8.90 GB/s external memory bandwidth and improve CABAC rate by 50%. A 7.14MB three-level memory hierarchy is designed to support internal 43.38 GB/s bandwidth and 13-port accesses, and reduces external reference frame bandwidth down to 2.97 GB/s. High complexity mode decision is supported with CFBAC rate estimator.
  • Keywords
    video codecs; video coding; CABAC; CFBAC rate estimator; H.265 encoder chip; frame-level pipelining; high complexity mode decision; high efficiency video coding; single-chip HEVC; Bandwidth; Complexity theory; Discrete cosine transforms; Filtering; Pipeline processing; Random access memory; Video coding; HEVC; UHDTV; high complexity mode decision; memory hierarchy; pipeline; video encoder;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2013 Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4673-5531-5
  • Type

    conf

  • Filename
    6578657
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=629992