DocumentCode :
630011
Title :
A 12Gb/s 0.92mW/Gb/s forwarded clock receiver based on ILO with 60MHz jitter tracking bandwidth variation using duty cycle adjuster in 65nm CMOS
Author :
Young-Ju Kim ; Lee-Sup Kim
Author_Institution :
KAIST, Daejeon, South Korea
fYear :
2013
fDate :
12-14 June 2013
Abstract :
This paper presents a quarter-rate forwarded clock (FC) receiver based on an injection-locked oscillator (ILO) which exploits a phenomenon that phases of the output clock are shifted by the duty cycle of an injection clock. To utilize this phase shifting phenomenon, a simple duty cycle adjuster (DCA) is proposed. By using the DCA, the proposed FC receiver achieves 760MHz of wide jitter tracking bandwidth (JTB) while consuming 11mW. Furthermore, it has only 60MHz JTB variation which is reduced by 74% compared to the conventional ILO in spite of clock deskew. The test chip achieves 12Gb/s data rate with 0.92mW/Gb/s in a 1V 65nm CMOS process.
Keywords :
CMOS analogue integrated circuits; UHF integrated circuits; UHF oscillators; VHF oscillators; clocks; injection locked oscillators; integrated circuit testing; jitter; CMOS process; DCA; FC; ILO; JTB; bandwidth 60 MHz; bit rate 12 Gbit/s; clock deskew; duty cycle adjuster; frequency 760 MHz; injection clock; injection-locked oscillator; jitter tracking bandwidth variation; phase shifting phenomenon; power 11 mW; quarter-rate forwarded clock receiver; size 65 nm; test chip; voltage 1 V; Clocks; Computer architecture; Frequency control; Jitter; Microprocessors; Receivers; Very large scale integration; Forwarded clock architecture; duty cycle adjuster; injection-locked oscillator; receiver;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
Type :
conf
Filename :
6578676
Link To Document :
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