A 0.36V, 33.3 µ W 18-band ANSI S1.11 1/3-octave filter bank for digital hearing aids in 40nm CMOS

Author

Jinn-Shyan Wang ; Keng-Jui Chang ; Tay-Jyi Lin ; Prasojo, Richard Wu ; Chingwei Yeh

Author_Institution

Dept. of EE, Nat. Chung Cheng Univ. (CCU), Chiayi, Taiwan

fYear

2013

fDate

12-14 June 2013

Abstract

This paper presents an ultra-low-power filter bank design for digital hearing aids. A novel time borrow & local boost (TBLB) scheme for aggressive voltage over-scaling is proposed, which does not incur cycle penalty on the rescue of timing violations, and is thus suitable for hardwired ASIC. The measured power of the test chips with the straightforward filter implementation can outperform those with extensive algorithmic or numerical optimizations.

Keywords

ANSI standards; CMOS digital integrated circuits; application specific integrated circuits; channel bank filters; hearing aids; integrated circuit testing; low-power electronics; 18-Band ANSI S1.11 1/3-Octave Filter Bank; CMOS; TBLB scheme; digital hearing aids; hardwired ASIC; numerical optimizations; power 33.3 muW; size 40 nm; test chips; time borrow & local boost; timing violations; ultra-low-power filter bank design; voltage 0.36 V; voltage over-scaling; Filter banks; Flip-flops; Latches; Power measurement; Semiconductor device measurement; Timing; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578684