Title :
A 1.59Gpixel/s motion estimation processor with −211-to-211 search range for UHDTV video encoder
Author :
Jinjia Zhou ; Dajiang Zhou ; Gang He ; Goto, Satoshi
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
Abstract :
A motion estimation (ME) processor for H.264 encoder is implemented in 40nm CMOS. With algorithm and architecture co-optimization, its throughput reaches 1.59Gpixel/s for 7680×4320p 48fps video, at least 7.5 times faster than previous chips. Its core power dissipation is 622mW at 210MHz, with energy efficiency improved by 23%. DRAM bandwidth requirement is reduced by 68%. With a maximum search range of ±211 (horizontal) by ±106 (vertical) around a predictive search center, the proposed ME processor well accommodates the large motion of ultra-high-resolution video.
Keywords :
CMOS integrated circuits; DRAM chips; high definition television; microprocessor chips; motion estimation; video codecs; CMOS technology; DRAM; H.264 encoder; UHDTV video encoder; architecture co-optimization; frequency 210 MHz; motion estimation processor; power 622 mW; predictive search center; size 40 nm; ultra-high-resolution video; Bandwidth; Belts; Encoding; Random access memory; Throughput; Vectors; Video coding;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
