A 69dB SNDR, 25MHz BW, 800MS/s continuous-time bandpass ΔΣ ADC using DAC duty cycle control for low power and reconfigurability

A new power-efficient, reconfigurable, 6^th-order continuous-time bandpass delta-sigma modulator architecture is presented. A new duty-cycle-controlled DAC halves the number of DACs in the modulator, and also enables the center frequency to be reconfigurable. A prototype 800MS/s modulator achieves 69dB SNDR with a 25MHz bandwidth at a 200MHz IF. The center frequency can be varied from 180MHz to 220MHz. The 65nm CMOS prototype consumes 35mW and occupies a die area of 0.25mm².