Title :
A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS
Author :
Jiangfeng Wu ; Chou, Alvin ; Cheng-Hsun Yang ; Yen Ding ; Yen-Jen Ko ; Sha-Ting Lin ; Wenbo Liu ; Chi-Ming Hsiao ; Ming-Hung Hsieh ; Chun-Cheng Huang ; Juo-Jung Hung ; Kwang Young Kim ; Le, Matthew ; Tianwei Li ; Wei-Ta Shih ; Shrivastava, Ashish ; Yau-Ch
Author_Institution :
Broadcom Corp., Irvine, CA, USA
Abstract :
A 5.4GS/s 12b 2-way interleaved pipeline ADC is presented. To achieve high speed, a complementary switched-capacitor amplifier is proposed, along with ping-pong amplifier sharing and digital MDAC equalization. The ADC achieves 61dB SNR and 57dB THD up to 2.6GHz input frequency at 5.4GS/s, consumes 500mW and occupies 0.4mm2 area in 28nm CMOS.
Keywords :
CMOS analogue integrated circuits; amplifiers; analogue-digital conversion; equalisers; pipeline processing; switched capacitor networks; 2-way interleaved pipeline ADC; CMOS; bit rate 5.4 Gbit/s; complementary switched-capacitor amplifier; digital MDAC equalization; noise figure 61 dB; ping-pong amplifier sharing; power 500 mW; CMOS integrated circuits; Frequency measurement; MOS devices; Pipelines; Signal to noise ratio; Switches; Topology;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
