Title :
A 70MS/s 69.3dB SNDR 38.2fJ/conversion-step time-based pipelined ADC
Author :
Taehwan Oh ; Venkatram, H. ; Un-Ku Moon
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
Abstract :
A Nyquist ADC with time-based pipelined architecture is proposed. The proposed hybrid pipeline stage, incorporating time-domain amplification based on a charge pump, enables power efficient analog to digital conversion. The proposed ADC also adopts a minimalist switched amplifier with 24dB open-loop dc gain in the first stage MDAC that is based on a new V-T operation, instead of a conventional high gain amplifier. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 69.3dB at 6.38mW power, with a near rail-to-rail 1MHz input of 2.4VP-P at 70MHz sampling frequency and 1.3V supply. This results in 38.2fJ/conversion-step FOM.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; charge pump circuits; pipeline processing; switched networks; CMOS technology; FOM; Nyquist ADC; analog-digital converters; charge pump; conversion step time based pipelined ADC; figure of merit; frequency 70 MHz; gain 24 dB; hybrid pipeline stage; minimalist switched amplifier; pipelined architecture; power 6.38 mW; size 0.13 mum; time-domain amplification; voltage 1.3 V; voltage 2.4 V; Capacitors; Frequency measurement; Gain; Linearity; Pipeline processing; Time-domain analysis; Tin;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
