Process and local layout effect interaction on a high performance planar 20nm CMOS

As technology has advanced, layout dependent device parameter shifts are becoming more influential to the actual circuit operation and performance, such that design style differences could create systematic device variability due to layout unless those effect are minimized and well captured in the device model[1]. In this paper, we characterize the device layout effects on a high performance planar 20nm CMOS technology for low power mobile applications [2], and demonstrate a layout effect reduction by optimizing key process elements while improving device performance. Nfet/pfet boundary proximity in Replacement Metal Gate (RMG), Length of active area (LOD or SA/SB) and gate pitch dependency are discussed in terms of Stress Memorization Technique (SMT) and embedded SiGe (eSiGe) processes.