0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Author

Nomura, M. ; Muramatsu, Ayumi ; Takeno, H. ; Hattori, Saki ; Ogawa, D. ; Nasu, M. ; Hirairi, K. ; Kumashiro, S. ; Moriwaki, S. ; Yamamoto, Yusaku ; Miyano, S. ; Hiraku, Y. ; Hayashi, Isao ; Yoshioka, Kazuaki ; Shikata, Akira ; Ishikuro, Hiroki ; Ahn, M. ;

Author_Institution

Semicond. Technol. Acad. Res. Center (STARC), Yokohama, Japan

fYear

2013

fDate

12-14 June 2013

Abstract

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.

Keywords

CMOS integrated circuits; buffer circuits; clock distribution networks; image processing; logic circuits; logic design; microprocessor chips; parallel processing; power convertors; AFS; CMOS technology; HVCD; SIMD; adaptive frequency scaling; buck converters; frequency 10 MHz; frequency 7.5 MHz; high voltage clock distribution; hold buffers; image processor; logic circuit design; power 4.26 mW; power 9 mW; size 40 nm; voltage 0.5 V; word length 32 bit; Central Processing Unit; Clocks; Delays; Energy efficiency; Frequency measurement; Logic circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578745