FDSOI process/design full solutions for ultra low leakage, high speed and low voltage SRAMs

Author

Ranica, R. ; Planes, N. ; Weber, Olivier ; Thomas, O. ; Haendler, S. ; Noblet, D. ; Croain, D. ; Gardin, C. ; Arnaud, F.

Author_Institution

STMicroelectron., Crolles, France

fYear

2013

fDate

12-14 June 2013

Abstract

We propose for the first time a complete SRAM offer in FDSOI technology, covering low leakage, high speed and low voltage customer requirements, through simple and innovative process/design solutions. Starting from a bulk-design direct porting, we evidenced +50% and +200% bead at Vdd=lV and 0.6V, respectively vs 28LP bulk. Additionally, -100mV Vmin reduction has been demonstrated with 28FDSOI. Alternative flip-well and single well architecture provides further speed and Vmin improvement, down to 0.42V on 1Mb 0.197μm². Ultimate stand-by leakage below lpA on 0.120μm² bitcell at Vdd=0.6V is finally reached by taking the full benefits of the back bias capability of FDSOI.

Keywords

SRAM chips; silicon-on-insulator; 28FDSOI; 28LP bulk; SRAM; back bias capability; bulk-design direct porting; flip-well architecture; fully-depleted SOI design full solutions; low voltage customer requirements; single well architecture; speed improvement; ultra low leakage customer requirements; voltage 0.6 V; voltage 1 V; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578752