Title :
A 22nm 2.5MB slice on-die L3 cache for the next generation Xeon® Processor
Author :
Wei Chen ; Szu-Liang Chen ; Siufu Chiu ; Ganesan, Rajeshwari ; Lukka, Venkata ; Mar, Wei Wing ; Rusu, Stefan
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The 20-way set associative 2.5MB slice ported L3 cache for the multi-core Xeon® Processor uses 0.108 um2 cell in a 22nm tri-gate technology with 2.7TB maximum bandwidth. It is protected by double-error correction/triple-error detection ECC. The basic building block is designed to support floorplan style on each processor with large L3 cache. On die fuse storage enables high resolution repair coverage. Programmable transient voltage collapse writes assist (TVC-WA), wordline underdrive read assist (WLUD-RA) circuits (RWA) is used to achieve aggressive Vccmin goal. Per-die post silicon RWA fusing and per-die post silicon redundancy flow have significantly improved L3 cache Vccmin by more than 150mv.Shutoff per slice features has reduced SRAM leakage.
Keywords :
SRAM chips; cache storage; circuit layout; content-addressable storage; elemental semiconductors; error correction; error detection; multiprocessing systems; silicon; transients; 20-way set associative slice ported L3 cache; SRAM leakage; Si; TVC-WA; WLUD-RA circuit; die fuse storage; double-error correction/triple-error detection ECC; floorplan style; high resolution repair coverage; maximum bandwidth; multicore Xeon processor; next generation Xeon processor; per-die post silicon RWA; per-die post silicon redundancy flow; programmable transient voltage collapse writes assist; size 22 nm; slice on-die L3 cache; trigate technology; wordline underdrive read assist; Arrays; Fuses; Random access memory; Redundancy; Silicon; Switching circuits; Transistors;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
