Residual errors in coplanar on-chip 1-port calibration caused by standard deviations

The uncertainty calculation for on-wafer 1-port S-Parameter measurements due to the uncertainty of coplanar on-chip calibration standards is presented. Analytical expressions for the sensitivities are used and applied for typical fabrication tolerances of monolithic integrated on-chip structures. The method is verified for OSM calibration by means of simulations with a commercial calibration software as well as by measurements, where test-structures with artificial errors were used. In each case the analytically calculated deviation is compared to a numerical approach and good agreement is found. All results are given for a MMIC process on GaAs, but can be adopted for other technologies.