Register allocation for high-level synthesis of hardware accelerators targeting FPGAs

This work evaluates the benefits of several register allocation strategies as part of a design flow for automatic generation of application-specific hardware accelerators targeting FPGAs. As usage of vendor-specific design tools is mandatory for system designs targeting FPGAs, high-level synthesis has to account for the optimization capabilities already implemented in these design tools. In addition, FPGA-specific hardware characteristics have to be considered as well. Therefore, several register allocation strategies are evaluated in the context of a GCC based C to HDL design flow for application-specific hardware accelerators. Evaluation was done by means of several example designs from typical application domains for embedded systems. These designs were synthesized using the ISE design suite with either area or speed as an optimization criteria. Synthesis results for Spartan 6 and Artix 7 FPGAs show that with regards to clock frequency and area requirements, register allocation strategy should be kept simple when generating HDL code as an input for FPGA vendor-specific design tools.