Analysis and design considerations of systematic nonlinearity for sigma-delta current-steering DAC

Author

Irfansyah, Astria Nur ; Lehmann, T. ; Jenkins, J. ; Hamilton, Tara J.

Author_Institution

Sch. of Electr. Eng. & Telecommun., Univ. of New South Wales, Sydney, NSW, Australia

fYear

2013

fDate

17-19 April 2013

Firstpage

108

Lastpage

111

Abstract

This paper deals with the design aspect of current-steering D/A converters which is to be incorporated in an oversampling sigma-delta DAC with Dynamic Element Matching (DEM), and particularly with the trade-off between device sizing, output impedance, and ideal systematic non-linearity. A formula for the estimation of minimum output impedance requirement based on DNL specification is proposed, and the corresponding design guideline is given. As a case study, a 16-bit sigma-delta current-steering DAC is presented. It is shown in this paper that basic cascode current mirror structure is not practical for this purpose. An 8-level current steering DAC with 16-bit accuracy was designed in a 0.18-μm CMOS process using the regulated cascode enhanced output impedance current mirror. A worst case INL of 0.09 LSB of a 16-bit converter was achieved.

Keywords

CMOS integrated circuits; digital-analogue conversion; 8-level current steering DAC; CMOS process; DEM; DNL specification; cascode current mirror structure; current-steering D/A converters; device sizing; dynamic element matching; output impedance; output impedance current mirror; sigma-delta current-steering DAC; size 0.18 mum; systematic nonlinearity; word length 16 bit; Accuracy; Finite element analysis; Impedance; Linearity; Mathematical model; Mirrors; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON Spring Conference, 2013 IEEE

Conference_Location

Sydney, NSW

Print_ISBN

978-1-4673-6347-1

Type

conf

DOI

10.1109/TENCONSpring.2013.6584427

Filename

6584427