VLSI architecture of multiplier-less DWT image processor

High performance digital image processing is considered a significant contributes of high performance embedded computing and signal processing projects. In this paper, we have provided the design and implementation of VLSI architecture of multiplier-less DWT image processor. The filter coefficients multiplication is resolved by simple shift and adds. Multi-resolution features of bi-orthogonal DWT and a new scheme of reading images from memory are employed to reduce the memory requirements. The image is processed by the overlapped blocks without dividing the image into sub blocks. The experimental results are provided for power, area and hardware utilization. The proposed design is smaller and faster than designs with multiplier based designs. This is, to our knowledge, the first hardware design paper that provides BDWT image processor from theory description to the front-end synthesis.