Optimal Vth window in endurance and retention enhancement of MLC flash

In FLASH memory, Multi-level Chip (MLC) allowed increased storage capacity without increasing the die size, therefore it was cost-per-bit reduction for any given fabrication technology. Multi-level product needs requirement of a smaller Vth distribution and less noise margins between levels. A wider Vth window is associated with higher programming voltage and higher electric fields results in more disturb in reliability. In this paper, according to failure analysis result optimization of MLC Vth window to enhance the reliability of retention and Endurance test was studied on 40nm Multi-Level Chip Flash cells.