FFT Architectures for Real-Valued Signals Based on Radix- $2^{3}$ and Radix- $2^{4}$ Algorithms

This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals. The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths. The imaginary parts of the computations replace the redundant operations in the modified flow graph. New butterfly structures are designed to handle the hybrid datapaths. The proposed hybrid datapath leads to a general approach which can be extended to all radix- 2ⁿ based FFT algorithms. Further, architectures with arbitrary level of parallelism can be derived using the folding methodology. Novel 2-parallel and 4-parallel architectures are presented for radix- 2³ and radix- 2⁴ algorithms. The proposed architectures maximize the utilization of hardware components with no redundant computations. The proposed radix- 2³ and radix- 2⁴ architectures lead to low hardware complexity with respect to adders and delays. The N-point 4-parallel radix- 2⁴ architecture requires 2(log₁₆N-1) complex multipliers, 2log²N real adders and N complex delay elements.