Conquering variability in mixed-signal ICs

Summary form only given: Shrinking feature sizes in IC manufacturing are required for implementing Moore´s law of doubling device density. Higher device density enables increasing digital IC performance. For mixed-signal ICs, shrinking transistor size implies increasing variability of analog device parameters. This has prevented analog circuit designs to benefit from shrinking process geometries. At the same time, increasing (digital) performance causes increasing customer expectations also regarding analog performance parameters. Conquering the effects of increased variability is an engineering challenge. Trimming and calibration is a design solution to this challenge. However, the cost incurred during IC manufacturing can become a significant part of the overall product cost, especially, when trimming is performed as part of product test. Design-for-Test (DfT) is a key for reducing the cost of product test by providing test access mechanisms and built-in self-tests. Extending DfT to Design-for-Trimming and Calibration is part of Dialog Semiconductor´s approach to design challenges for the next generation ICs. In this contribution, we show-case examples of bridging between design and test for the implementation of mixed-signal ICs used in mobile communication platforms.