DocumentCode :
634646
Title :
A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes
Author :
Al Hariri, Alaa Aldin ; Monteiro, Fabrice ; Sieler, L. ; Dandache, A.
Author_Institution :
Lab. LCOMS, Univ. de Lorraine, Metz, France
fYear :
2013
fDate :
8-10 July 2013
Firstpage :
163
Lastpage :
166
Abstract :
In this paper, we are proposing a new architecture for fast encoding of Quasi-Cyclic Low-Density Parity Codes (QC-LDPC). QC-LDPC codes are becoming more and more popular in a wide range of applications, including data transmission (WiMAX, DVB-S2) in telecommunication systems, increasing the need for effective encoder architectures. In our approach, support for a large subset of QC-LDPC codes is provided thanks to the configurability of the architecture at synthesis level. High levels of parallelism can be reached, and hence high throughput achieved, due to the modular encoder architecture that takes advantage of the highly regular structure of QC-LDPC parity check matrices. The architectural design has been validated through implementation on an Altera Stratix II FPGA of different encoders related to DVB-T2 and DVB-S2. Very high data rates (up to 28.9 GB/s) have been achieved with still acceptable hardware consumption (about 32k logic elements) proving the effectiveness of the approach.
Keywords :
cyclic codes; data communication; digital video broadcasting; field programmable gate arrays; logic design; parallel architectures; parity check codes; Altera Stratix II FPGA; DVB-S2; DVB-T2; QC-LDPC codes; QC-LDPC parity check matrices; WiMAX; architectural design validation; data rates; data transmission; hardware consumption; high-throughput configurable parallel encoder architecture configurability; logic elements; modular encoder architecture; quasicyclic low-density parity-check codes; synthesis level; Digital video broadcasting; Encoding; Field programmable gate arrays; Hardware; Parity check codes; Standards; Throughput; Error correcting codes; FPGA implementation; QC-LDPC; parallel and configurable encoder architectures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International
Conference_Location :
Chania
Type :
conf
DOI :
10.1109/IOLTS.2013.6604069
Filename :
6604069
Link To Document :
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