A systematic generation of optimized heterogeneous 3D Networks-on-Chip architecture

In this paper, we present a novel algorithm which systematically generates heterogeneous three-dimensional Networks-on-Chips (3D NoCs) topologies for a given application such that the vertical connections as well as the communication energy is reduced while the NoC performance is maintained. The proposed algorithm analyzes the target application and generates heterogeneous architectures by efficiently redistributing the vertical links and buffer spaces based on the vertical link and buffer utilization. The algorithm has been evaluated by synthetic and various real-world traffic patterns. Experimental results show that the proposed algorithm generates optimized architectures with lower energy consumption and significant reduction in packet delays compared to the existing 3D NoC architectures.