Runtime adaptation on dataflow HPC platforms

We are facing an ever growing quest for performance in High Performance Computing (HPC) systems. The growing concerns for the power budgets and overall deployment costs required to run these systems are opening new ways to novel high performance computing platforms. New paradigms and architectures are being developed to tackle these challenges. In this context, FPGA-based HPC platforms employed to accelerate algorithms expressed as data flow programs are a promising paradigm. One traditional limiting factor of FPGA technology is that the ever increasing complexity of the applications might require the designer to switch to a bigger device or, conversely, the same device might be underutilized due to difficulties at sharing the available logic. Partial Reconfiguration is the standard technique to overcome such limitations. This paper presents the research work done during the technology transfer to extend the Maxeler design flow to efficiently support Partial Reconfiguration (PR). In this work we focus on the design and development of a methodology to support the PR feature in the Maxeler design flow, a commercially successful FPGA-based HPC platform, showing the advantages of such an approach on the resulting platform.