Modeling and calibration of ADP process for inductance calculation with InductEx

Author

Fourie, Christoff ; Xizhu Peng ; Takahashi, Asami ; Yoshikawa, N.

Author_Institution

Dept. of Electr. & Electron. Eng., Stellenbosch Univ., Stellenbosch, South Africa

fYear

2013

fDate

7-11 July 2013

Firstpage

1

Lastpage

3

Abstract

The AIST advanced process (ADP2), with 9 Nb layers and 1 μm minimum Josephson junction size is currently the most complex low-Tc superconductive integrated circuit fabrication process in operation. With planarization for all layers below the main ground plane, and conductors that may traverse several layers, modeling inductance for numerical calculation requires special attention to the capabilities of the extraction tool. We present specific improvements made to InductEx to model the ADP process, including support for selective layer planarization, multiple ground planes and conductors below a ground plane. We discuss calibration of extracted values to experimental results, and show results for pulse transfer cells with inductive coupling and isolated ground planes.

Keywords

integrated circuit manufacture; numerical analysis; superconducting integrated circuits; ADP2; AIST advanced process; InductEx; Josephson junction; inductance calculation; inductive coupling; numerical calculation; selective layer planarization; size 1 mum; superconductive integrated circuit fabrication; Couplings; Inductance; Integrated circuit modeling; Niobium; Planarization; Semiconductor device modeling; Superconductivity; ground plane modeling; inductance calculation; inductex; planarization; three-dimensional modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International

Conference_Location

Cambridge, MA

Print_ISBN

978-1-4673-6369-3

Type

conf

DOI

10.1109/ISEC.2013.6604270

Filename

6604270