Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design

Three-dimensional (3D) integration with through-silicon vias (TSVs) is promising in the integration of many cores into a single chip. Network-on-chip (NoC) can efficiently manage the complicated 3D interconnections. However, irregular and dense TSV arrays used as vertical links in 3D NoC cause severe TSV height variation during silicon-thinning and chemical-mechanical polishing (CMP) processes. It may lead to TSV bonding failure between silicon layers. In this paper, we propose the first CMP-aware application-specific 3D NoC design that minimizes such TSV height variation and thus reduces the bonding failure, and meanwhile optimizes conventional NoC design objectives such as hop count, wirelength, power consumption, and area. Our 3D NoC design assigns cores to proper silicon layers, determines the 3D NoC topology, allocates routing paths, and then floorplans all cores, routers, and TSV arrays in a CMP-aware manner. The key idea behind this 3D NoC design flow is to determine the CMP-aware 3D NoC topology where TSV arrays with low and uniform metal density are inserted between adjacent layers. Experimental results show that our CMP-aware 3D NoC design achieves, on average, 17.9% lower TSV height variation, 15% lower hop count, 2.3% shorter total wirelength, and 7.8% lower power consumption than the previous state-of-the-art 3D NoC designs.