60-GHz transceivers in nano-scale CMOS technology for WirelessHD standard applications

This paper reports a system-level study of a 60-GHz wireless system for uncompressed high-definition video communications. The study is addressed to explore the implementation of 60-GHz transceivers in nano-scale CMOS technology. A model of the high data rate physical layer based on the specification released by the consortium WirelessHD has been implemented in MATLAB and the system simulations of the bit error rate have been carried out in order to derive the specifications of the 60-GHz transceiver building blocks. The specifications have been derived by taking into account the capabilities of the 65nm CMOS technology. System simulations take into account also transceiver nonidealities, including the power amplifier nonlinearity, local oscillator phase noise and receiver noise figure. The study also considers phased array implementations. This study, confirms the opportunity offered by nano-scale CMOS process as enabling technology for the implementation of 60-GHz transceivers for wireless high-definition uncompressed video communication system.