Dealing with the over-pessimism in ASIC physical design flow

A multi-million instance ASIC design with clocks frequencies up-to 1GHz, employing automatic synthesis & layout methods, looks for every accuracy improvement in optimization and timing verification. This paper introduces two techniques to improve this accuracy. The first technique is the delay derate method. In this method, the implementation tool is provided with a global multiplier that reduces the interconnect delay of all interconnect timing arcs in the design. This technique helps to improve the design timing by reducing the number of buffers/inverters in the design. The additional advantages are reduction in the run time, area and power. The second technique improves accuracy in the timing verification by employing signoff STA (Static Timing Analysis) tool in the early stages of the physical design. The method provides an average timing improvement of 30% per cell stage, a significant performance boost for the critical timing paths.