An FPGA based stereoptic image capture system

Stereopsis, the perception of depth of an object within a scene viewed from two different points is often modelled in an effort to generate three-dimensional information from a dual image capture. This paper presents an FPGA based hardware prototype of a stereoscopic capture system using a pair of CMOS image sensors. Data buffering and pipelining methods are employed using FPGA control of embedded SRAM and DPRAM memory. Captured realtime dual image data is displayed on a VGA display and concurrently transferred, via USB, to a host PC, enabling the development of host-based 3D image processing algorithms. Concurrent migration of data from image sensor pair to VGA, C++, and MATLAB is demonstrated.