Parallel implementation of high resolution radar signal processing system based on multi-IC architecture

In this paper, a pulsed doppler (PD) radar signal processing algorithm designed to track targets with high velocity is implemented in hardware based on 4 ADSP-TS201 TigerSHARC processors and 4 XC4VSX55. Both the radar signal processing algorithm and hardware architecture are proposed. To map the algorithm effectively, pipeline optimization on system and instruction levels are adopted, and various factors are taken into consideration, such as system complexity, balance of the task in each processor, communication between processors. Practical experiment proves that both the design of this hardware platform and the realization of algorithm are effective, real-time and reliable.