Implementation of parallel interface and matrix transpose for SAR imaging based on Virtex6 FPGA

This paper is mainly devoted to discuss design method of synthetic aperture radar (SAR) real-time signal processing based on FPGA, and this method has been verified on the hardware platform. Account for SAR real-time imaging, huge data must be stored in external memory such as DDR SDRAM. The effective bandwidth will be greatly reduced which has a great impact on the whole system efficiency, if traditional method is used. In this paper, an effective and realizable approach is put forward to improve the efficiency of matrix transpose. Furthermore, in order to realize communication between different boards, LVDS is chosen and it can better guarantee the performance of the whole system. The implementation of LVDS interface design is illustrated to realize high-speed real-time transmission and link multiple FPGA on one board in the paper.