DocumentCode :
641832
Title :
Design of spaceborne SAR imaging processing and fast Verification Based on FPGA
Author :
Liu Jin ; Chen Liang ; Liu Ying ; Xie Yizhuang
Author_Institution :
Radar Res. Lab., BeiJing Inst. of Techonlogy, Beijing, China
fYear :
2013
fDate :
14-16 April 2013
Firstpage :
1
Lastpage :
5
Abstract :
Realization of real-time processing for spaceborne synthetic aperture radar (SAR) based on FPGA is a tough work because of its complicated algorithm, huge data and difficulty of debugging on board. This paper first analyses the characteristic of FPGA and puts forward fast pulse compression architecture. System-level simulation of FPGA software for spaceborne SAR is carried out by the new way of system verification techniques. According to the hardware environment, system-level simulation model is composed of system input and output, high speed memory interface and DSP interface. Fast debugging for spaceborne SAR imaging software is implemented and its validity has been verified.
Keywords :
field programmable gate arrays; pulse compression; radar imaging; spaceborne radar; DSP interface; FPGA software; fast verification; forward fast pulse compression architecture; real-time processing; spaceborne SAR image processing; spaceborne synthetic aperture radar; system level simulation; FPGA; pulse compression; spaceborne SAR; system-level simulation;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Radar Conference 2013, IET International
Conference_Location :
Xi´an
Electronic_ISBN :
978-1-84919-603-1
Type :
conf
DOI :
10.1049/cp.2013.0420
Filename :
6624584
Link To Document :
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