Event-driven analog-to-digital converter with conversion-speed-centric architecture and activity-dependent power consumption

The paper presents a concept of an event-driven analog-to-digital converter accepting irregular conversion demands with conversion-speed-centric architecture and activity-dependent power consumption. The proposed converter architecture based on a binary-scaled capacitor array uses a technique of event-driven successive charge redistribution and allows overlapping of a conversion of the previous sample and a capture of the next sample. The general condition on proper converter operation is that the consecutive conversion demands have to be spaced at least by the interval equal to the maximum conversion time. In particular, the proposed converter can be used for time-to-digital conversion in the asynchronous Sigma-Delta ADCs. In the paper, the lower bound on charge redistribution rate for a given Sigma-Delta modulation depth is derived.