A low power analog RAM implementation for in-probe beamforming in ultrasound imaging

Author

Sharma, Shantanu ; Ytterdal, Trond

Author_Institution

Dept. of Electron. & Telecommun., Norwegian Univ. of Sci. & Technol., Trondheim, Norway

fYear

2013

fDate

8-12 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

An Analog RAM architecture for beamforming based on switched current circuits is presented. The proposed architecture allows the sharing of the same bias current for different memory cells, hence results in a large amount of power saving. The beamformer consists of total 16 channels and in each channel a delay line with depth of 16 has been implemented. The input frequency is 10MHz and a sampling frequency of 25MHz is used. The proposed architecture achieves 50dB of dynamic range and 49dB of SNDR with power dissipation of 760μW for one channel. The ARAM is implemented in 180nm CMOS technology and occupies 250×150μm² per channel.

Keywords

CMOS memory circuits; acoustic signal processing; analogue processing circuits; array signal processing; random-access storage; switched current circuits; ultrasonic measurement; ultrasonic transducer arrays; CMOS technology; SNDR; analog RAM architecture; channel delay line; dynamic range; frequency 10 MHz; in probe beamforming; low power analog RAM implementation; memory cell bias current sharing; power dissipation; power saving; sixteen channel beamformer; size 150 mum; size 250 mum; switched current circuits; ultrasound imaging; Capacitors; Clocks; Computer architecture; Delay lines; Delays; Transistors; Ultrasonic imaging; Analog RAM; Beam forming; Low power; Ultrasound;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design (ECCTD), 2013 European Conference on

Conference_Location

Dresden

Type

conf

DOI

10.1109/ECCTD.2013.6662297

Filename

6662297