Hardware models for automated partitioning and mapping in multi-core systems

Multi-core CPUs offer several major benefits in mobile and embedded systems. For instance, they provide better energy efficiency and more computing power at the same clock speed compared to single-core CPUs. These benefits do not come for free: A program has to be divided into tasks, which can be executed in parallel on different cores. Partitioning of software and mapping on cores are nontrivial activities that require detailed knowledge about the multi-core CPU, e.g., if shared memories are available, their size, and other properties. Such programmers´ information about a CPU is typically stored in processor handbooks. If this information would be available in a machine readable model, we call it hardware model, the partitioning and mapping activities can be automated. In this paper, we propose a hardware model and illustrate it using an example of a Freescale multi-core CPU. We then discuss a small case study, which illustrates the use of the hardware model in partitioning, mapping, and code generation.