Optimisation and length scaling of raised drain buried oxide SOI tunnel FET

A detailed study of a tunnelling field-effect transistor using a SOI substrate with raised buried oxide in the drain is reported. The simulated device exhibits improved ON current, lower OFF current, high transconductance and better subthreshold swing with variations to gate length scaling. Moreover, it is immune to short channel effects such as drain-induced barrier narrowing, threshold voltage roll-off etc. The hetero-gate dielectric is used to reduce the parasitic bipolar current at the drain side and to increase the tunnelling generation rate at the source side. The study was carried out using the two-dimensional Synopsys TCAD tool.