A Unified Architecture for a Dual Field ECC Processor Applicable to AES

This paper presents a unified architecture for a dual field Elliptical curve cryptographic (ECC) Processor that can support the operations of both fields, Galois field GF(P) and GF(2m). In this work ECC performance is increased by proper selection of coordinates and arithmetic unit. ECC Arithmetic unit provides the function of Dual field multiplication and addition. Using Elliptical curve cryptography (ECC) key exchange algorithm, two symmetric keys are generated, which can be applied to any symmetric encryption algorithm like AES. Then, the encrypted plaintext is decrypted to get the original plaintext. Simulation is done using Xilinx 13.4 ISE simulator. The proposed Dual field ECC processor design shows that it can reach up to 124.347 MHz, consumes 1.091W power and Occupies 3,066 slices, which is implemented on Xilinx 13.4 Virtex 5 FPGA(Field Programmable Gate array) as a target device.