Triple well subthreshold CMOS logic using body-bias technique

Subthreshold logic provides extremely low power consumption since the power supplies are kept below the threshold voltage and using the small subthreshold current of MOS transistors to operate. Subthreshold circuits are ideal for ultra low power applications however they suffer from low operating speeds. By improving the speed of subthreshold circuits their application spectrum can be expanded. In this paper a body-bias technique in triple well CMOS technology is explored to match the subthreshold currents of both the NMOS and PMOS transistors for improving the speed of subthreshold circuits. We derive an approximate expression for the generated body bias voltage. Circuit simulations were conducted using 180nm CMOS technology to validate proposed concept. The results were compared with standard body bias technique in terms of delay and power consumption. The proposed body biasing technique improves power-delay product by approx. 38%.