Reconfigurable VLSI digital filters for tolerating multiple timing errors

One of the major problems with advanced semiconductor technology is timing errors caused by process variation and device aging. With such problems, conventional worst-case designs suffer poor system performance. This paper proposes an aggressive design technique for VLSI digital filters for tolerating timing errors. When a timing error occurs, the system reconfigures the buffer cell of the problematic stage with little performance degradation. We have applied the technique to several digital filters. The design of an IIR filter with tolerance of timing errors is described and demonstrated. The results show that our proposed design achieves tolerance of multiple timing errors with small cost of chip area and power consumption.