A new lightweight and high performance AES S-box using modular design

Composite field arithmetic (CFA) is often utilized to create compact AES S-box implementation. However, the resultant circuitry is complex with long critical path and it induces high dynamic power consumption. In this paper, we presented a new architectural optimization in CFA which enhances the speed performance of the compact AES S-box and reduces its dynamic power consumption at the same time. The proposed methodology transforms and partitions the three-level CFA isomorphism in AES S-box into modules of logic equations, consisting of AND and XOR gates. This approach produces a highly modular design that makes effective pipelining possible. In this study, we also presented a new GF(2⁴) multiplier for lightweight AES applications. For validation, the new AES S-box was implemented on Cyclone III EP2C5T144C6. It has a total of 66 logic elements (LEs), 36 registers and having maximum operating frequency of 346 MHz and a total dynamic power consumption of 1.84 mW.