DocumentCode
648524
Title
Testable combinational circuit design based on free ZDD-implementation of irredundant SOPof Boolean function
Author
Ostanin, S.
Author_Institution
Tomsk State Univ., Tomsk, Russia
fYear
2013
fDate
27-30 Sept. 2013
Firstpage
1
Lastpage
4
Abstract
It is found out that a set of test patterns for all multiple stuck-at faults at the CLBs poles of combinational circuit in the frame of FPGA technology coincides with the set of test for all single stuck-at faults of irredundant sum-of-products describing the combinational circuit behavior. The combinational circuit designed based on Free ZDD-implementation of irredundant sum-of-products.
Keywords
Boolean functions; combinational circuits; failure analysis; field programmable gate arrays; integrated circuit design; integrated circuit testing; Boolean function; CLB poles; FPGA technology; free ZDD-implementation; irredundant SOP; irredundant sum-of-products; multiple stuck-at faults; testable combinational circuit design;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium, 2013 East-West
Conference_Location
Rostov-on-Don
Print_ISBN
978-1-4799-2095-2
Type
conf
DOI
10.1109/EWDTS.2013.6673109
Filename
6673109
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