DocumentCode
648553
Title
Delay testable sequential circuit designs
Author
Matrosova, A. ; Mitrofanov, E. ; Singh, V.
Author_Institution
Tomsk State Univ., Tomsk, Russia
fYear
2013
fDate
27-30 Sept. 2013
Firstpage
1
Lastpage
4
Abstract
New method of a sequential circuit design based on using mixed description of the circuit behavior is suggested. A combinational part behavior of a sequential circuit is represented with the composition of ROBDDs (Reduced Ordered Binary Decision Diagrams) and monotonous products. The method provides fully delay testability of a combinational part of a sequential circuit. Algorithms of deriving test pairs for robust PDFs (Path Delay Faults) are suggested. The method is oriented to cut the path lengths of the obtained circuits.
Keywords
logic design; logic testing; sequential circuits; PDF; ROBDD; delay testable sequential circuit designs; monotonous products; path delay faults; reduced ordered binary decision diagrams;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium, 2013 East-West
Conference_Location
Rostov-on-Don
Print_ISBN
978-1-4799-2095-2
Type
conf
DOI
10.1109/EWDTS.2013.6673138
Filename
6673138
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