DocumentCode
648574
Title
Real-time interconnection network for single-chip many-core computers
Author
Richter, H.
Author_Institution
Clausthal Univ. of Technol., Clausthal-Zellerfeld, Germany
fYear
2013
fDate
27-30 Sept. 2013
Firstpage
1
Lastpage
4
Abstract
A real-time capable interconnection network for single chip many-core computers is presented that is superior to the known Benes network because its routing algorithm scales linearly with the number of switches, and because it has a modular setup which eases chip synthesis and test. Its routing is based on “separation and approximation”. This method can also be applied to the Benes network, thus making its looping routing obsolete.
Keywords
multiprocessing systems; multiprocessor interconnection networks; network routing; Benes network; approximation; chip synthesis; chip test; looping routing; modular setup; real-time interconnection network; routing algorithm; separation; single-chip many-core computers; switches; Benes Network; Looping Routing; Many-Core Computer; Real-time Network on Chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium, 2013 East-West
Conference_Location
Rostov-on-Don
Print_ISBN
978-1-4799-2095-2
Type
conf
DOI
10.1109/EWDTS.2013.6673159
Filename
6673159
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