Title :
Transaction level model of embedded processor for vector-logical analysis
Author :
Hahanova, I.V. ; Obrizan, Volodymyr ; Adamov, Alexander ; Shcherbin, Dmitry
Author_Institution :
Comput. Eng. Fac., Kharkov Nat. Univ. of Radioelectron., Kharkov, Ukraine
Abstract :
Transaction level model of embedded processor for improving the performance of logical relation analysis are proposed. It is based on the hardware implementation of vector operations. There are examples of the model using for the semantics analysis of Russian adjectives. The embedded processor was designed to be part of SoC that will be implemented on FPGA.
Keywords :
embedded systems; field programmable gate arrays; hardware description languages; natural language processing; object-oriented programming; system-on-chip; FPGA; Russian adjectives; SoC; embedded processor; natural language structure analysis; object-oriented programming; semantics analysis; system Verilog transaction level model; vector-logical analysis;
Conference_Titel :
Design & Test Symposium, 2013 East-West
Conference_Location :
Rostov-on-Don
Print_ISBN :
978-1-4799-2095-2
DOI :
10.1109/EWDTS.2013.6673169
