Title :
PDF testability of the circuits derived by special covering ROBDDs with gates
Author :
Matrosova, A. ; Nikolaeva, E. ; Kudin, D. ; Singh, V.
Author_Institution :
Tomsk State Univ., Tomsk, Russia
Abstract :
Circuits obtained by covering ROBDD nodes with special gate subcircuits are considered. Formulae derived from their structural descriptions are investigated. Based on the results of investigations algorithms of deriving test pairs for robust testable PDFs and validatable non robust testable PDFs of such circuits are developed. Possibilities of cutting calculations under finding the longest circuit paths are discussed.
Keywords :
binary decision diagrams; circuit testing; delay circuits; logic circuits; logic gates; PDF circuit testability; ROBDD node; gate subcircuit; path delay fault; reduced and ordered binary decision diagram; binary decision diagram (BDD); design for testability; path delay fault (PDF); robust testable PDF; validatable non robust testable PDF;
Conference_Titel :
Design & Test Symposium, 2013 East-West
Conference_Location :
Rostov-on-Don
Print_ISBN :
978-1-4799-2095-2
DOI :
10.1109/EWDTS.2013.6673183
