DocumentCode :
648629
Title :
Scheduling tests for 3D SoCs with temperature constraints
Author :
Rawat, Indira ; Gupta, M.K. ; Singh, V.
Author_Institution :
Dept. of Electr. Eng., Gov. Eng. Coll., Ajmer, India
fYear :
2013
fDate :
27-30 Sept. 2013
Firstpage :
1
Lastpage :
4
Abstract :
In this paper the test scheduling of 3D SoC has been considered taking the thermal aspect into account. The 3D SoC consists of a complete system stacked vertically. Each stack or layer can have many functional blocks and any floorplan. Test scheduling of the stacked layers has been considered. We have built up a 3D stack for an assumed floorplan. The floorplan for the different layers can be similar or different. The testing of each functional block or core is to be done. Testing will result in production of heat. Heat will spread to its neighboring blocks resulting in their temperature rise. If the testing is done sequentially then temperature rise will be more. Test scheduling is to be done such that the temperature rise does not exceed the limits.
Keywords :
integrated circuit testing; scheduling; system-on-chip; three-dimensional integrated circuits; 3D SoC; 3D stack; floorplan; heat production; stacked layers; temperature constraints; test scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design & Test Symposium, 2013 East-West
Conference_Location :
Rostov-on-Don
Print_ISBN :
978-1-4799-2095-2
Type :
conf
DOI :
10.1109/EWDTS.2013.6673214
Filename :
6673214
Link To Document :
بازگشت